1. Field of the Invention
The present invention relates to delay circuitry for delaying an input signal such as a clock, clock generating circuitry for generating a clock, and phase synchronization circuitry for bringing an input clock into synchronization with a reference signal.
2. Description of the Prior Art
Referring now to FIG. 13, there is illustrated a block diagram showing the structure of prior art clock generating circuitry (or phase synchronization circuitry) for generating an output clock in synchronization with an input clock using a phase locked loop or PLL, the frequency of the output clock being either the same as or multiple times as large as that of the input clock. In the figure, reference numeral 1 denotes a voltage-controlled oscillator or VCO, 3 denotes a frequency divider for dividing an output clock from the VCO 1, the output clock having a frequency that is multiple times as large as that of the input clock, 4 denotes an oscillator for generating a reference clock as an input clock, 6 denotes a charge pump for comparing the phase of the frequency-divided clock from the frequency divider 3 with that of the reference clock from the oscillator 4 and for generating and furnishing a control voltage having a value corresponding to the difference between the phases of the frequency-divided clock and reference clock to make them in phase with each other, 8 denotes an inverter included in the VCO 1, and 9 denotes a PLL.
In operation, the VCO 1 generates an output clock having a frequency that is n-times as large as that of the reference clock, and then furnishes the output clock to the frequency divider 3 as well as to outside the clock generating circuitry. The frequency divider 3 divides the frequency of the output clock to generate and furnish a frequency-divided clock to the charge pump 6. The charge pump 6 then compares the phase of the frequency-divided clock from the frequency divider 3 with that of the reference clock from the oscillator 4 and generates a control signal having a value corresponding to the phase difference between the phases of the frequency-divided clock and reference clock to bring them into synchronization with each other. To be more specific, when the frequency-divided clock leads the reference clock, the charge pump 6 increases the value or voltage of the control signal. Otherwise, the charge pump 6 decreases the value or voltage of the control signal. When the frequency-divided clock from the frequency divider 3 is brought into synchronization with or made in phase with the reference clock from the oscillator 4, the PLL 9 brings itself into its locked state. When the PLL 9 makes a transition to its locked state, the frequency-divided clock, which has been obtained by dividing the output of the VCO 1 by n by means of the frequency divider 3, becomes equal to the reference clock in pulse repetition period.
The PLL 9 can include a plurality of dividers 3. In this case, the prior art clock generating circuitry makes it possible to change between frequency multiplication ratios and set the frequency multiplication ratio defined by the VCO to a desired one by selecting one frequency divider 3 from among the plurality of dividers according to the desired frequency multiplication ratio. For example, when the frequency multiplication ratio selected is 1:n, the PLL 9 generates an output clock having a frequency that is n-times as large as that of the reference clock. Furthermore, the prior art clock generating circuitry can include a plurality of oscillators 4. The clock generating circuitry can change the frequency of the reference clock by selecting one oscillator 4 from among the plurality of oscillators. The clock generating circuitry thus can change the pulse repetition rate of the output clock by switching between the plurality of dividers 3 and/or switching between the plurality of oscillators 4. However, when carrying out such switching, there is a need to bring the PLL into its locked state again because the switching brings the PLL into its unlocked state, thus increasing the time required for changing the pulse repetition period of the output clock. In order to reduce the time required for changing the pulse repetition period of the output clock, a prior art method is disclosed, the method comprising the steps of generating a plurality of clocks having difference pulse repetition periods using a plurality of oscillators 4 and a plurality of PLLs 9, as shown in FIG. 14, and selecting one clock from among the plurality of clocks using a multiplexer 10. However, this prior art method has no alternative but to increase the size of the circuitry in order to adjust the pulse repetition period of the output clock over a wide range and in steps of a fine time step. In addition, the prior art method suffers from a drawback that changing the pulse repetition period of the output clock causes a phase shift or the like and hence a jitter in the output clock.
Referring next to FIG. 15, there is illustrated a block diagram showing the structure of an example of prior art delay circuitry capable of adjusting a time delay that the circuitry provides for an input. In the figure, reference numeral 11 denotes an inverter, 12 denotes a multiplexer, 19 denotes a register, and 46 denotes the delay circuitry. As shown in FIG. 15, the delay circuitry 46 includes a plurality of inverters 11 connected in series, the number of inverters 11 being even. The plurality of inverters 11 in series are divided into a plurality of sets each including two inverters, and a plurality of lead lines disposed at intervals of one set of two inverters and two other lead lines from two ends of the series of plural inverters 11 are connected to the multiplexer 12. The multiplexer 12 can change the time delay by selecting one lead line from among the plurality of lead lines according to the contents of the register 19. The use of a PLL including the delay circuitry as shown in FIG. 15 makes it possible to adjust the pulse repetition period of an output clock. However, this method has a disadvantage that it cannot change the time delay in steps of an arbitrary time step other than the time step determined by a gate delay, the time delay may change due to a change in the ambient temperature or a change in the voltage of a power supply, and therefore it cannot change the pulse repetition period of the output clock in steps of a precise time step.
Referring next to FIG. 16, there is illustrated a block diagram showing the structure of other prior art delay circuitry, in which a plurality of delay circuits are connected in series in order to adjust the time delay provided by the delay circuitry over a wide range and in steps of a fine time step. As shown in FIG. 16, when two delay circuits 46a and 46b are connected in series, for example, the first delay circuit 46a can be so constructed as to adjust the time delay in steps of a small time step and the second delay circuit 46b can be so constructed as to adjust the time delay in steps of a large time step. The time delays provided by the first and second delay circuits 46a and 46b are defined by lower and upper bits of the register 19, respectively. In this case, the first delay circuit 46a can have eight time delay settings, and, when the time delay provided by any two inverters 11 in the first delay circuit 46a is .DELTA.d and the time delay provided by any two inverters 11 in the second delay circuit 46b is .DELTA.D, .DELTA.D must be equal to (.DELTA.d.times.8). It is, however, impossible to make .DELTA.D equal to (.DELTA.d.times.8) at all times because of a change in the voltage of a power supply or a change in the ambient temperature, or a variation in the manufacturing process. Unless .DELTA.D is equal to (.DELTA.d.times.8) at all times, the smallest change in the time delay provided by the delay circuitry can become greater than .DELTA.d. Furthermore, there is a possibility that even though the contents of the register 19 are varied so that the delay time is increased, the delay time actually decreases.
Referring next to FIG. 17, there is illustrated a block diagram showing the structure of other prior art delay circuit as disclosed in Japanese Patent Application Publication (KOKAI) No. 59-63822, for example. In the figure, reference numeral 50 denotes a phase/frequency comparator for comparing the phase or frequency of a reference clock applied thereto with that of a frequency-divided clock from a frequency divider 3, and 51 denotes a loop filter and level shifter for generating a control signal from the output of the phase/frequency comparator 50, and for furnishing the control signal to a VCO 1 and a delay line 53.
In operation, the VCO 1 furnishes its output to the frequency divider 3, and the frequency divider 3 divides the frequency of the output. The frequency divider 3 then furnishes a frequency-divided clock to the phase/frequency comparator 50. The phase/frequency comparator 50 compares the phase or frequency of the frequency-divided clock with that of the reference clock. The phase/frequency comparator 50 then furnishes its output to the loop filter and level shifter 51. The loop filter and level shifter 51 furnishes a control signal to the delay line 53. The control signal has a value that indicates the phase difference between the phases of the reference clock and frequency-divided clock, and that varies according to the pulse signal from the phase/frequency comparator 50. The control signal is also applied to the delay line 53. The time delay provided by the delay line 53 is thus set to a predetermined value according to the control signal.
A problem with the prior art clock generating circuitry as shown in FIG. 13 is that since the PLL included in the circuitry defines the pulse repetition period of the output clock based on the frequency multiplication of the input clock and the frequency division of the frequency-multiplied clock, it cannot adjust the pulse repetition period of the output clock over a wide range and in steps of a fine time step.
A problem with the prior art delay circuitry as shown in FIG. 15 is that since the time delay may change due to a variation in the manufacturing process or a change in environmental factors, it cannot precisely define the time delay in steps of a certain time step, thus not being able to provide clock generating circuitry that can precisely set the pulse repetition period and phase of the output clock in steps of a certain time step.
A problem with the other prior art delay circuitry as shown in FIG. 16, in which a plurality of delay circuits are connected in series to adjust the time delay provided by the delay circuitry over a wide range and in steps of a fine time step, is that since it is impossible to keep the time delay provided by each delay circuit constant at all times because of a change in the voltage of a power supply or a change in the ambient temperature, or a variation in the manufacturing process, the smallest change in the time delay provided by the delay circuitry can become greater than its original value and there is a possibility that a control performed for the time delay to increase conversely decreases the time delay.
A problem with the other prior art delay circuitry as shown in FIG. 17 is that although it can prevent the time delay from changing due to a variation in the manufacturing process or a change in environmental factors by forming each delay element included in the delay line 53 in the same manner that each delay element included in the VCO 1 is formed, it cannot freely change the time delay in steps of a time step.